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banco_reg rodando com testbench

master
guilmour 7 months ago
parent
commit
87ee31290b
8 changed files with 188 additions and 7 deletions
  1. +1
    -0
      .~lock.notas.ods#
  2. BIN
      notas.ods
  3. BIN
      vhdl_3/banco_reg/banco_reg.ghw
  4. +33
    -0
      vhdl_3/banco_reg/banco_reg.gtkw
  5. +2
    -2
      vhdl_3/banco_reg/banco_reg.vhd
  6. +134
    -0
      vhdl_3/banco_reg/banco_reg_tb.vhd
  7. +9
    -2
      vhdl_3/banco_reg/make.sh
  8. +9
    -3
      vhdl_3/banco_reg/work-obj93.cf

+ 1
- 0
.~lock.notas.ods# View File

@@ -0,0 +1 @@
Guilmour Rossi,guilmour,lars.cosmos,24.10.2019 21:49,file:///home/guilmour/.config/libreoffice/4;

BIN
notas.ods View File


BIN
vhdl_3/banco_reg/banco_reg.ghw View File


+ 33
- 0
vhdl_3/banco_reg/banco_reg.gtkw View File

@@ -0,0 +1,33 @@
[*]
[*] GTKWave Analyzer v3.3.79 (w)1999-2017 BSI
[*] Fri Oct 25 01:40:25 2019
[*]
[dumpfile] "/home/guilmour/gits/csw30/vhdl_3/banco_reg/banco_reg.ghw"
[dumpfile_mtime] "Fri Oct 25 01:38:34 2019"
[dumpfile_size] 3771
[savefile] "/home/guilmour/gits/csw30/vhdl_3/banco_reg/banco_reg.gtkw"
[timestart] 0
[size] 1366 708
[pos] -1 -1
*-29.180727 400000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] top.
[treeopen] top.banco_reg_tb.
[treeopen] top.banco_reg_tb.uut.
[treeopen] top.banco_reg_tb.uut.reg1.
[sst_width] 207
[signals_width] 253
[sst_expanded] 1
[sst_vpaned_height] 194
@24
#{top.banco_reg_tb.w_data[15:0]} top.banco_reg_tb.w_data[15] top.banco_reg_tb.w_data[14] top.banco_reg_tb.w_data[13] top.banco_reg_tb.w_data[12] top.banco_reg_tb.w_data[11] top.banco_reg_tb.w_data[10] top.banco_reg_tb.w_data[9] top.banco_reg_tb.w_data[8] top.banco_reg_tb.w_data[7] top.banco_reg_tb.w_data[6] top.banco_reg_tb.w_data[5] top.banco_reg_tb.w_data[4] top.banco_reg_tb.w_data[3] top.banco_reg_tb.w_data[2] top.banco_reg_tb.w_data[1] top.banco_reg_tb.w_data[0]
@28
#{top.banco_reg_tb.w_addr[2:0]} top.banco_reg_tb.w_addr[2] top.banco_reg_tb.w_addr[1] top.banco_reg_tb.w_addr[0]
top.banco_reg_tb.clk
top.banco_reg_tb.w_en
top.banco_reg_tb.rst
@22
#{top.banco_reg_tb.uut.reg1.registro[15:0]} top.banco_reg_tb.uut.reg1.registro[15] top.banco_reg_tb.uut.reg1.registro[14] top.banco_reg_tb.uut.reg1.registro[13] top.banco_reg_tb.uut.reg1.registro[12] top.banco_reg_tb.uut.reg1.registro[11] top.banco_reg_tb.uut.reg1.registro[10] top.banco_reg_tb.uut.reg1.registro[9] top.banco_reg_tb.uut.reg1.registro[8] top.banco_reg_tb.uut.reg1.registro[7] top.banco_reg_tb.uut.reg1.registro[6] top.banco_reg_tb.uut.reg1.registro[5] top.banco_reg_tb.uut.reg1.registro[4] top.banco_reg_tb.uut.reg1.registro[3] top.banco_reg_tb.uut.reg1.registro[2] top.banco_reg_tb.uut.reg1.registro[1] top.banco_reg_tb.uut.reg1.registro[0]
@25
#{top.banco_reg_tb.uut.reg1.data_in[15:0]} top.banco_reg_tb.uut.reg1.data_in[15] top.banco_reg_tb.uut.reg1.data_in[14] top.banco_reg_tb.uut.reg1.data_in[13] top.banco_reg_tb.uut.reg1.data_in[12] top.banco_reg_tb.uut.reg1.data_in[11] top.banco_reg_tb.uut.reg1.data_in[10] top.banco_reg_tb.uut.reg1.data_in[9] top.banco_reg_tb.uut.reg1.data_in[8] top.banco_reg_tb.uut.reg1.data_in[7] top.banco_reg_tb.uut.reg1.data_in[6] top.banco_reg_tb.uut.reg1.data_in[5] top.banco_reg_tb.uut.reg1.data_in[4] top.banco_reg_tb.uut.reg1.data_in[3] top.banco_reg_tb.uut.reg1.data_in[2] top.banco_reg_tb.uut.reg1.data_in[1] top.banco_reg_tb.uut.reg1.data_in[0]
[pattern_trace] 1
[pattern_trace] 0

+ 2
- 2
vhdl_3/banco_reg/banco_reg.vhd View File

@@ -21,12 +21,12 @@ entity banco_reg is

-- Read A
RA_addr : in unsigned(2 downto 0);
RA_en : in std_logic;
-- RA_en : in std_logic;
RA_data : out unsigned(15 downto 0);

-- Read B
RB_addr : in unsigned(2 downto 0);
RB_en : in std_logic;
-- RB_en : in std_logic;
RB_data : out unsigned(15 downto 0)
);
end entity;

+ 134
- 0
vhdl_3/banco_reg/banco_reg_tb.vhd View File

@@ -0,0 +1,134 @@
-- para ajudar a entender banco de registradores
-- ou register file em inglês: https://www.youtube.com/watch?v=S7jsgT1U5II
-- imagem: https://i.imgur.com/4O8fsio.png

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity banco_reg_tb is
end entity;

architecture a_banco_reg_tb of banco_reg_tb is
component banco_reg
port(
clk : in std_logic;
rst : in std_logic;

-- 2 downto 0 porque sao 8 registradores
-- 15 downto 0 porque sao registradores de 16 bits

-- Write
W_addr : in unsigned(2 downto 0);
W_en : in std_logic;
W_data : in unsigned(15 downto 0);

-- Read A
RA_addr : in unsigned(2 downto 0);
-- RA_en : in std_logic;
RA_data : out unsigned(15 downto 0);

-- Read B
RB_addr : in unsigned(2 downto 0);
-- RB_en : in std_logic;
RB_data : out unsigned(15 downto 0)
);
end component;

signal clk, rst, W_en: std_logic;
signal RA_addr, RB_addr, W_addr: unsigned(2 downto 0);
signal RA_data, RB_data, W_data: unsigned(15 downto 0);


begin
uut: banco_reg
port map(
clk => clk,
rst => rst,
W_en => W_en,
RA_addr => RA_addr,
RB_addr => RB_addr,
W_addr => W_addr,
RA_data => RA_data,
RB_data => RB_data,
W_data => W_data
);

process
begin
W_en <= '0';
wait for 50 ns;
W_en <= '1';
wait for 50 ns;
end process;

process
begin
clk <= '0';
wait for 50 ns;
clk <= '1';
wait for 50 ns;
end process;

process -- sinal de reset
begin
rst <= '0';
wait for 380 ns;
rst <= '1';
wait for 20 ns;
end process;

process -- sinais dos casos de teste
begin
-- salvar 218 no reg1
RA_addr <= "000";
RB_addr <= "111";
W_addr <= "010";
W_data <= "0000000011011010";
wait for 100 ns;

RA_addr <= "111";
RB_addr <= "100";
W_addr <= "000";
W_data <= "0010001011001010";
wait for 100 ns;

RA_addr <= "100";
RB_addr <= "110";
W_addr <= "000";
W_data <= "1110001011001010";
wait for 100 ns;

RA_addr <= "001";
RB_addr <= "001";
W_addr <= "100";
W_data <= "1110001011111111";
wait for 100 ns;

RA_addr <= "000";
RB_addr <= "111";
W_addr <= "010";
W_data <= "0000000011011010";
wait for 100 ns;

RA_addr <= "111";
RB_addr <= "100";
W_addr <= "000";
W_data <= "0010001011001010";
wait for 100 ns;

RA_addr <= "100";
RB_addr <= "110";
W_addr <= "000";
W_data <= "1110001011001010";
wait for 100 ns;

RA_addr <= "001";
RB_addr <= "001";
W_addr <= "100";
W_data <= "1110001011111111";
wait for 100 ns;

wait;
end process;
end architecture;

+ 9
- 2
vhdl_3/banco_reg/make.sh View File

@@ -1,6 +1,7 @@
#!/bin/bash

echo "${1}"
echo "${2}"

clear

@@ -10,6 +11,12 @@ read -n 1 -s -r -p "Press any key to continue"
echo " "
echo " "

echo "ghdl -a ${2}.vhd"
ghdl -a ${2}.vhd
read -n 1 -s -r -p "Press any key to continue"
echo " "
echo " "


echo "ghdl -e ${1}"
ghdl -e ${1}
@@ -30,13 +37,13 @@ echo " "
echo " "

echo "ghdl -r ${1}_tb --wave=${1}.ghw"
ghdl -r ${1}_tb --wave=${1}.ghw
ghdl -r ${1}_tb --stop-time=3000ns --wave=${1}.ghw
read -n 1 -s -r -p "Press any key to continue"
echo " "
echo " "

echo "gtkwave ${1}.ghw"
gtkwave ${1}.ghw
gtkwave ${1}.ghw --save=${1}.gtkw
read -n 1 -s -r -p "Press any key to continue"
echo " "
echo " "

+ 9
- 3
vhdl_3/banco_reg/work-obj93.cf View File

@@ -1,4 +1,10 @@
v 4
file . "banco_reg.vhd" "2d307283cd45360d42c4d3457967c6054421b4f0" "20191025005400.023":
entity banco_reg at 5( 169) + 0 on 11;
architecture a_banco_reg of banco_reg at 34( 812) + 0 on 12;
file . "banco_reg.vhd" "1c2fab222435150a920484e499dae9f814c13cf4" "20191025013832.054":
entity banco_reg at 5( 169) + 0 on 47;
architecture a_banco_reg of banco_reg at 34( 818) + 0 on 48;
file . "banco_reg_tb.vhd" "439d2f89d823a6173669a4143922456b5c1f9938" "20191025013833.493":
entity banco_reg_tb at 5( 169) + 0 on 51;
architecture a_banco_reg_tb of banco_reg_tb at 12( 275) + 0 on 52;
file . "reg16bits.vhd" "353d7073627e45f7d5f5cbc8dc53b572430c3b21" "20191025013832.634":
entity reg16bits at 1( 0) + 0 on 49;
architecture a_reg16bits of reg16bits at 15( 290) + 0 on 50;

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