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banco de registradores metade

master
guilmour 4 months ago
parent
commit
909fe85f0a
4 changed files with 71 additions and 13 deletions
  1. +1
    -0
      .gitignore
  2. +30
    -0
      reg16bits.vhd
  3. +10
    -13
      vhdl_3/banco_reg/banco_reg.vhd
  4. +30
    -0
      vhdl_3/banco_reg/reg16bits.vhd

+ 1
- 0
.gitignore View File

@@ -0,0 +1 @@
PC_gus_old

+ 30
- 0
reg16bits.vhd View File

@@ -0,0 +1,30 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity reg16bits is
port(
clk : in std_logic;
rst : in std_logic;
wr_en : in std_logic;
data_in : in unsigned(15 downto 0);
data_out : out unsigned(15 downto 0)
);
end entity;

architecture a_reg16bits of reg16bits is
signal registro: unsigned(15 downto 0);
begin
process(clk, rst, wr_en)
begin
if rst = '1' then
registro <= "0000000000000000";
elsif wr_en = '1' then
if rising_edge(clk) then
registro <= data_in;
end if;
end if;
end process;
data_out <= registro; -- conexão direta, fora do processo

end architecture;

+ 10
- 13
vhdl_3/banco_reg/banco_reg.vhd View File

@@ -29,18 +29,15 @@ entity banco_reg is
end entity;

architecture a_banco_reg of banco_reg is
signal registro: unsigned(15 downto 0);
begin
process(clk, rst, wr_en)
begin
if rst = '1' then
registro <= "0000000000000000";
elsif wr_en = '1' then
if rising_edge(clk) then
registro <= data_in;
end if;
end if;
end process;
data_out <= registro; -- conexão direta, fora do processo
component reg16bits is
port(
clk : in std_logic;
rst : in std_logic;
wr_en : in std_logic;
data_in : in unsigned(15 downto 0);
data_out : out unsigned(15 downto 0)
);
end component;
reg0: reg16bits port map(clk);

end architecture;

+ 30
- 0
vhdl_3/banco_reg/reg16bits.vhd View File

@@ -0,0 +1,30 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity reg16bits is
port(
clk : in std_logic;
rst : in std_logic;
wr_en : in std_logic;
data_in : in unsigned(15 downto 0);
data_out : out unsigned(15 downto 0)
);
end entity;

architecture a_reg16bits of reg16bits is
signal registro: unsigned(15 downto 0);
begin
process(clk, rst, wr_en)
begin
if rst = '1' then
registro <= "0000000000000000";
elsif wr_en = '1' then
if rising_edge(clk) then
registro <= data_in;
end if;
end if;
end process;
data_out <= registro; -- conexão direta, fora do processo

end architecture;

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