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reaging files

master
guilmour 7 months ago
parent
commit
94c37983f1
30 changed files with 418 additions and 0 deletions
  1. +0
    -0
      assembly_1/mips1.asm
  2. +0
    -0
      assembly_1/mips2.asm
  3. +0
    -0
      assembly_1/mips3.asm
  4. +0
    -0
      assembly_1/mips4.asm
  5. +0
    -0
      assembly_1/mips5.asm
  6. +0
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      assembly_1/oi.txt
  7. +0
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      assembly_2/ex_02.txt
  8. +0
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      assembly_2/mips1.asm
  9. +0
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      assembly_2/mips2.asm
  10. +0
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      assembly_2/oit.xt
  11. +0
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      assembly_2/rascunho.txt
  12. BIN
      vhdl_1/porta/porta.ghw
  13. +16
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      vhdl_1/porta/porta.vhd
  14. +47
    -0
      vhdl_1/porta/porta_tb.vhd
  15. +7
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      vhdl_1/porta/work-obj93.cf
  16. BIN
      vhdl_1/somador/somador.ghw
  17. +17
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      vhdl_1/somador/somador.vhd
  18. +51
    -0
      vhdl_1/somador/somador_tb.vhd
  19. +7
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      vhdl_1/somador/work-obj93.cf
  20. BIN
      vhdl_1/uprocessador-1-v31.pdf
  21. BIN
      vhdl_2/decoder/decoder.ghw
  22. +23
    -0
      vhdl_2/decoder/decoder.vhd
  23. +58
    -0
      vhdl_2/decoder/decoder_tb.vhd
  24. +7
    -0
      vhdl_2/decoder/work-obj93.cf
  25. +42
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      vhdl_2/mux2x1/make.sh
  26. BIN
      vhdl_2/mux2x1/mux.ghw
  27. +20
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      vhdl_2/mux2x1/mux.vhd
  28. +116
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      vhdl_2/mux2x1/mux_tb.vhd
  29. +7
    -0
      vhdl_2/mux2x1/work-obj93.cf
  30. BIN
      vhdl_2/uprocessador-2-v35.pdf

Lesson_1/mips1.asm → assembly_1/mips1.asm View File


Lesson_1/mips2.asm → assembly_1/mips2.asm View File


Lesson_1/mips3.asm → assembly_1/mips3.asm View File


Lesson_1/mips4.asm → assembly_1/mips4.asm View File


Lesson_1/mips5.asm → assembly_1/mips5.asm View File


Lesson_1/oi.txt → assembly_1/oi.txt View File


Lesson_2/ex_02.txt → assembly_2/ex_02.txt View File


Lesson_2/mips1.asm → assembly_2/mips1.asm View File


Lesson_2/mips2.asm → assembly_2/mips2.asm View File


Lesson_2/oit.xt → assembly_2/oit.xt View File


Lesson_2/rascunho.txt → assembly_2/rascunho.txt View File


BIN
vhdl_1/porta/porta.ghw View File


+ 16
- 0
vhdl_1/porta/porta.vhd View File

@@ -0,0 +1,16 @@
library ieee;
use ieee.std_logic_1164.all;

entity porta is
port( in_a : in std_logic;
in_b : in std_logic;
a_e_b : out std_logic
);
end entity;


architecture a_porta of porta is
begin
a_e_b <= in_a and in_b;

end architecture;

+ 47
- 0
vhdl_1/porta/porta_tb.vhd View File

@@ -0,0 +1,47 @@
library ieee;
use ieee.std_logic_1164.all;

entity porta_tb is
-- port( in_a : in std_logic;
-- in_b : in std_logic;
-- a_e_b : out std_logic
-- );
end entity;


architecture a_porta_tb of porta_tb is
component porta
port(
in_a : in std_logic;
in_b : in std_logic;
a_e_b : out std_logic
);
end component;
signal in_a, in_b, a_e_b: std_logic;
begin
uut: porta port map
(
in_a => in_a,
in_b => in_b,
a_e_b => a_e_b
);
process
begin
in_a <= '0';
in_b <= '1';
wait for 50 ns;

in_a <= '1';
in_b <= '0';
wait for 50 ns;

in_a <= '1';
in_b <= '1';
wait for 50 ns;

in_a <= '0';
in_b <= '0';
wait for 50 ns;
wait;
end process;
end architecture;

+ 7
- 0
vhdl_1/porta/work-obj93.cf View File

@@ -0,0 +1,7 @@
v 4
file . "porta.vhd" "9f16c3c7f623615fc74da5ba1ac6cb18913a5707" "20190919173054.301":
entity porta at 1( 0) + 0 on 13;
architecture a_porta of porta at 12( 162) + 0 on 14;
file . "porta_tb.vhd" "e83ce4bfe558adbc78ec73ff6a1213594ab77927" "20190919174442.132":
entity porta_tb at 1( 0) + 0 on 17;
architecture a_porta_tb of porta_tb at 12( 180) + 0 on 18;

BIN
vhdl_1/somador/somador.ghw View File


+ 17
- 0
vhdl_1/somador/somador.vhd View File

@@ -0,0 +1,17 @@
library ieee;
use ieee.std_logic_1164.all;

entity somador is
port(
a : in std_logic;
b : in std_logic;
res : out std_logic; -- result
c_out : out std_logic -- carry out
);
end entity;

architecture a_somador of somador is
begin
res <= a or b;
c_out <= a and b;
end architecture;

+ 51
- 0
vhdl_1/somador/somador_tb.vhd View File

@@ -0,0 +1,51 @@
library ieee;
use ieee.std_logic_1164.all;

entity somador_tb is
-- port(
-- a : in std_logic;
-- b : in std_logic;
-- res : out std_logic; -- result
-- c_out : out std_logic -- carry out
-- );
end entity;

architecture a_somador_tb of somador_tb is
component somador
port(
a : in std_logic;
b : in std_logic;
res : out std_logic; -- result
c_out : out std_logic -- carry out
);
end component;

signal a, b, res, c_out : std_logic;
begin
uut: somador port map
(
a => a,
b => b,
res => res,
c_out => c_out
);
process
begin
a <= '0';
b <= '0';
wait for 50 ns;

a <= '0';
b <= '1';
wait for 50 ns;

a <= '1';
b <= '1';
wait for 50 ns;

a <= '1';
b <= '0';
wait for 50 ns;
wait;
end process;
end architecture;

+ 7
- 0
vhdl_1/somador/work-obj93.cf View File

@@ -0,0 +1,7 @@
v 4
file . "somador_tb.vhd" "c0c903c6b1bf0aff139755bf987c71dd602e0569" "20190919222510.600":
entity somador_tb at 1( 0) + 0 on 53;
architecture a_somador_tb of somador_tb at 13( 228) + 0 on 54;
file . "somador.vhd" "f4f651482ee99b2e60aa4556384d2701cfa979e4" "20190919222507.173":
entity somador at 1( 0) + 0 on 51;
architecture a_somador of somador at 13( 207) + 0 on 52;

BIN
vhdl_1/uprocessador-1-v31.pdf View File


BIN
vhdl_2/decoder/decoder.ghw View File


+ 23
- 0
vhdl_2/decoder/decoder.vhd View File

@@ -0,0 +1,23 @@
library ieee;
use ieee.std_logic_1164.all;

entity decoder is
port(
a : in std_logic;
b : in std_logic;

x0 : out std_logic;
x1 : out std_logic;
x2 : out std_logic;
x3 : out std_logic
);

end entity;

architecture a_decoder of decoder is
begin
x0 <= not a and not b;
x1 <= not a and b;
x2 <= a and not b;
x3 <= a and b;
end architecture;

+ 58
- 0
vhdl_2/decoder/decoder_tb.vhd View File

@@ -0,0 +1,58 @@
library ieee;
use ieee.std_logic_1164.all;

entity decoder_tb is
-- port(
-- a : in std_logic;
-- b : in std_logic;
--
-- x0 : out std_logic;
-- x1 : out std_logic;
-- x2 : out std_logic;
-- x3 : out std_logic
-- );
end entity;

architecture a_decoder_tb of decoder_tb is
component decoder
port(
a : in std_logic;
b : in std_logic;
x0 : out std_logic;
x1 : out std_logic;
x2 : out std_logic;
x3 : out std_logic
);
end component;

signal a, b, x0, x1, x2, x3 : std_logic;
begin
uut: decoder port map
(
a => a,
b => b,
x0 => x0,
x1 => x1,
x2 => x2,
x3 => x3
);
process
begin
a <= '0';
b <= '0';
wait for 50 ns;

a <= '0';
b <= '1';
wait for 50 ns;

a <= '1';
b <= '0';
wait for 50 ns;

a <= '0';
b <= '0';
wait for 50 ns;
wait;
end process;
end architecture;

+ 7
- 0
vhdl_2/decoder/work-obj93.cf View File

@@ -0,0 +1,7 @@
v 4
file . "decoder.vhd" "5fe436cd64e364542c40378dcd188bcca40ae249" "20190919213531.520":
entity decoder at 1( 0) + 0 on 21;
architecture a_decoder of decoder at 17( 229) + 0 on 22;
file . "decoder_tb.vhd" "22820e4347921426f421bd3cd3df77c72fe01922" "20190919214320.780":
entity decoder_tb at 1( 0) + 0 on 27;
architecture a_decoder_tb of decoder_tb at 16( 259) + 0 on 28;

+ 42
- 0
vhdl_2/mux2x1/make.sh View File

@@ -0,0 +1,42 @@
#!/bin/bash

echo "${1}"

clear

echo "ghdl -a ${1}.vhd"
ghdl -a ${1}.vhd
read -n 1 -s -r -p "Press any key to continue"
echo " "
echo " "


echo "ghdl -e ${1}"
ghdl -e ${1}
read -n 1 -s -r -p "Press any key to continue"
echo " "
echo " "

echo "ghdl -a ${1}_tb.vhd"
ghdl -a ${1}_tb.vhd
read -n 1 -s -r -p "Press any key to continue"
echo " "
echo " "

echo "ghdl -e ${1}_tb"
ghdl -e ${1}_tb
read -n 1 -s -r -p "Press any key to continue"
echo " "
echo " "

echo "ghdl -r ${1}_tb --wave=${1}.ghw"
ghdl -r ${1}_tb --wave=${1}.ghw
read -n 1 -s -r -p "Press any key to continue"
echo " "
echo " "

echo "gtkwave ${1}.ghw"
gtkwave ${1}.ghw
read -n 1 -s -r -p "Press any key to continue"
echo " "
echo " "

BIN
vhdl_2/mux2x1/mux.ghw View File


+ 20
- 0
vhdl_2/mux2x1/mux.vhd View File

@@ -0,0 +1,20 @@
library ieee;
use ieee.std_logic_1164.all;

entity mux is
port(
a : in std_logic;
b : in std_logic;
sel : in std_logic;
enable : in std_logic;

x : out std_logic
);
end entity;

architecture a_mux of mux is
begin
x <= a when sel='0' and enable='1' else
b when sel='1' and enable='1' else
'0';
end architecture;

+ 116
- 0
vhdl_2/mux2x1/mux_tb.vhd View File

@@ -0,0 +1,116 @@
library ieee;
use ieee.std_logic_1164.all;

entity mux_tb is
-- port(
-- a : in std_logic;
-- b : in std_logic;
-- sel : in std_logic;
-- enable : in std_logic;
--
-- x : out std_logic
-- );
end entity;

architecture a_mux_tb of mux_tb is
component mux
port(
a : in std_logic;
b : in std_logic;
sel : in std_logic;
enable : in std_logic;
x : out std_logic
);
end component;

signal a, b, sel, x, enable: std_logic;

begin
uut: mux port map
(
a => a,
b => b,
sel => sel,
enable => enable,
x => x
);

process
begin
a <= '0';
b <= '0';
enable <= '0';
sel <= '0';
wait for 50 ns;

a <= '0';
b <= '1';
enable <= '0';
sel <= '0';
wait for 50 ns;

a <= '1';
b <= '0';
enable <= '0';
sel <= '0';
wait for 50 ns;

a <= '0';
b <= '0';
enable <= '0';
sel <= '0';
wait for 50 ns;

-- com enable e sel 0
a <= '0';
b <= '0';
sel <= '0';
enable <= '1';
wait for 50 ns;

a <= '0';
b <= '1';
sel <= '0';
enable <= '1';
wait for 50 ns;

a <= '1';
b <= '0';
sel <= '0';
enable <= '1';
wait for 50 ns;

a <= '0';
b <= '0';
sel <= '0';
enable <= '1';
wait for 50 ns;

-- com enable e sel 1
a <= '0';
b <= '0';
sel <= '1';
enable <= '1';
wait for 50 ns;

a <= '0';
b <= '1';
sel <= '1';
enable <= '1';
wait for 50 ns;

a <= '1';
b <= '0';
sel <= '1';
enable <= '1';
wait for 50 ns;

a <= '0';
b <= '0';
sel <= '1';
enable <= '1';
wait for 50 ns;
wait;
end process;

end architecture;

+ 7
- 0
vhdl_2/mux2x1/work-obj93.cf View File

@@ -0,0 +1,7 @@
v 4
file . "mux_tb.vhd" "674d9f3853d6444c7a6b89254f726fdc9ee87562" "20191010002626.066":
entity mux_tb at 1( 0) + 0 on 43;
architecture a_mux_tb of mux_tb at 15( 253) + 0 on 44;
file . "mux.vhd" "7c65306a58aacf00efe61baaec044ecad534128e" "20191010002623.886":
entity mux at 1( 0) + 0 on 41;
architecture a_mux of mux at 15( 225) + 0 on 42;

BIN
vhdl_2/uprocessador-2-v35.pdf View File


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