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working on lab 3 vhdl reg

master
guilmour 7 months ago
parent
commit
cb23d6d344
11 changed files with 102 additions and 1 deletions
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      .~lock.notas.ods#
  2. BIN
      notas.ods
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      vhdl_2/ula/ula.ghw
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      vhdl_2/ula/ula.vhd
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      vhdl_2/ula/ula_tb.vhd
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      vhdl_2/ula/work-obj93.cf
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      vhdl_3/reg16bits/make.sh
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      vhdl_3/reg16bits/reg16bits.vhd
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      vhdl_3/reg8bits/make.sh
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      vhdl_3/reg8bits/reg8bits.vhd
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      vhdl_3/uprocessador-3-v33.pdf

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.~lock.notas.ods# View File

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Guilmour Rossi,guilmour,lars.cosmos,17.10.2019 13:44,file:///home/guilmour/.config/libreoffice/4;

BIN
notas.ods View File


ula/ula.ghw → vhdl_2/ula/ula.ghw View File


ula/ula.vhd → vhdl_2/ula/ula.vhd View File


ula/ula_tb.vhd → vhdl_2/ula/ula_tb.vhd View File


ula/work-obj93.cf → vhdl_2/ula/work-obj93.cf View File


ula/make.sh → vhdl_3/reg16bits/make.sh View File


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vhdl_3/reg16bits/reg16bits.vhd View File

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity reg16bits is
port(
clk : in std_logic;
rst : in std_logic;
wr_en : in std_logic;
data_in : in unsigned(15 downto 0);
data_out : in unsigned(15 downto 0)
);
end entity;

architecture a_reg16bits of reg16bits is
signal registro: unsigned(15 downto 0);
begin
process(clk, rst, wr_en)
begin
if rst = '1' then
registro <= "0000000000000000";
elsif wr_en = '1' then
if rising_edge(clk) then
registro <= data_in;
end if;
end if;
end process;
data_out <= registro; -- conexão direta, fora do processo

end architecture;

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vhdl_3/reg8bits/make.sh View File

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#!/bin/bash

echo "${1}"

clear

echo "ghdl -a ${1}.vhd"
ghdl -a ${1}.vhd
read -n 1 -s -r -p "Press any key to continue"
echo " "
echo " "


echo "ghdl -e ${1}"
ghdl -e ${1}
read -n 1 -s -r -p "Press any key to continue"
echo " "
echo " "

echo "ghdl -a ${1}_tb.vhd"
ghdl -a ${1}_tb.vhd
read -n 1 -s -r -p "Press any key to continue"
echo " "
echo " "

echo "ghdl -e ${1}_tb"
ghdl -e ${1}_tb
read -n 1 -s -r -p "Press any key to continue"
echo " "
echo " "

echo "ghdl -r ${1}_tb --wave=${1}.ghw"
ghdl -r ${1}_tb --wave=${1}.ghw
read -n 1 -s -r -p "Press any key to continue"
echo " "
echo " "

echo "gtkwave ${1}.ghw"
gtkwave ${1}.ghw
read -n 1 -s -r -p "Press any key to continue"
echo " "
echo " "

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vhdl_3/reg8bits/reg8bits.vhd View File

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity reg8bits is
port(
clk : in std_logic;
rst : in std_logic;
wr_en : in std_logic;
data_in : in unsigned(7 downto 0);
data_out : in unsigned(7 downto 0)
);
end entity;

architecture a_reg8bits of reg8bits is
signal registro: unsigned(7 downto 0);
begin
process(clk, rst, wr_en)
begin
if rst = '1' then
registro <= "00000000";
elsif wr_en = '1' then
if rising_edge(clk) then
registro <= data_in;
end if;
end if;
end process;
data_out <= registro; -- conexão direta, fora do processo
end architecture;

BIN
vhdl_3/uprocessador-3-v33.pdf View File


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