Material and exercises of Computer Organization and Architecture course at UTFPR.
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  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.numeric_std.all;
  4. entity reg16bits is
  5. port(
  6. clk : in std_logic;
  7. rst : in std_logic;
  8. wr_en : in std_logic;
  9. data_in : in unsigned(15 downto 0);
  10. data_out : out unsigned(15 downto 0)
  11. );
  12. end entity;
  13. architecture a_reg16bits of reg16bits is
  14. signal registro: unsigned(15 downto 0);
  15. begin
  16. process(clk, rst, wr_en)
  17. begin
  18. if rst = '1' then
  19. registro <= "0000000000000000";
  20. elsif wr_en = '1' then
  21. if rising_edge(clk) then
  22. registro <= data_in;
  23. end if;
  24. end if;
  25. end process;
  26. data_out <= registro; -- conexão direta, fora do processo
  27. end architecture;